Why this problem is hard — in the field's own words

[Intro — two or three paragraphs framing the interconnect thermal bottleneck: chips are wire-limited, wires are insulated by materials that trap heat, and the κ/ε∞ Pareto front (shown on the homepage) has been essentially static for decades. Then introduce the question this benchmark asks.]

The industry view

[Placeholder — full imec quote goes here, expanded from the homepage excerpt.]

[One or two paragraphs of context around the imec quote: their interconnect roadmap work and why they care about BEOL-compatible dielectrics.]

[Placeholder — full IBM quote goes here.]

[Context around the IBM quote.]

The academic view

[Placeholder — full professor quote goes here.]

[Context: what the theory community thinks about ML-driven inverse design, and where verified benchmarks fit versus generative-model papers.]

What a verified benchmark changes

[Closing argument: submissions graded by physics (DFT), novelty checked against Materials Project, recipes checked against real fab equipment, and the loop closed with an actual synthesis attempt. End with a call to action — explore the data, submit a model.]